Why packaging is important now

Packaging used to be an afterthought in the semiconductor manufacturing process, which was ignored by everyone. When you create this small piece of magic silicon chip, and then use some method to package it, and at the same time lead out the pins, a chip is born. But with the extension of Moore's Law, engineers realized that they could optimize and innovate all parts of the chip, including packaging, to produce the best products.

What is more surprising is that no packaging company was considered as important as the traditional front-end manufacturing process in the past. Encapsulated supply chain is usually considered as the "back end" and as a cost center, similar to the front and back office of the banking industry. But now, as the front-end is difficult to reduce the chip size better, a new area of concern has emerged, which is the emphasis on advanced packaging.

Next, let's discuss the development history of packaging, from simple DIP packaging to advanced 2.5D or 3D packaging.

Introduction to Packaging Development

This is a brief hierarchy of packaging technology I found in this wonderful video stand. If you have some time, you can have a look. (The video was published in 2012, but the latest 3D packaging technology was mentioned at that time, so it is not outdated.)

A simplified evolution process of packaging technology is: DIP>QFP>BGA>POP/SiP>WLP

Obviously, there are many different packaging technologies, but we want to discuss simple technologies that roughly represent each type, and then slowly bring them to the present. I also like the high-level overview below (although it is outdated, but still correct).

In the initial stage of packaging, the bare chip is usually sealed with ceramic or metal cans (airtight) to achieve maximum reliability. This is mainly applicable to aerospace and military applications, and these functions require the highest level of reliability. However, for most of our daily use cases, this is not really feasible, so we began to use plastic packaging and dual in-line packaging (DIP).

DIP packaging (1964-1980s)

The earliest DIP packaging element was invented by Bryant Buck Rogers of Fairchild Semiconductor in 1964. It was widely used in the ten years before surface mount technology came out. DIP uses plastic packaging shells around the actual bare chips (Editor's Note: In fact, a large number of military chips packaged with ceramics also use DIP packaging), and there are two rows of parallel protruding pins, called lead frames, which are connected to the following PCB (printed circuit board).

Resin, so it brings high reliability and low cost, and many of the first batch of landmark semiconductors are packaged in this way. Note that the chip is wired to the external lead frame, which makes it a "lead bonding" packaging method. This will be described in detail later.

Here's Intel 8008 -- actually one of the first modern microprocessors. Note its signature DIP encapsulation. Therefore, if you see fashionable photos of semiconductors that look like spiders, this is just a DIP packaged semiconductor.

Intel's original microprocessor, 8008 family

Then, each of these small gold pins is soldered to the PCB, where it contacts other electrical components and the rest of the system. The following is how the package is soldered to the PCB board.

PCB itself is usually laminated by copper or other electrical components from non-conductive materials. Then, the PCB board can transmit electrical signals from one place to another, and let the components connect and communicate with each other.

Although there are other deductive versions of DIP, it is actually time to turn to the next packaging technology paradigm or surface mount packaging that began in the 1980s.

Surface mount packaging (1980-1990)

The next step is not to install products through DIP, but to introduce surface mount technology (SMT). As implied, the package is directly mounted on the surface of the PCB, allowing more components to be used on a single substrate and reducing costs. The following figure shows a typical surface mount package.

There are many variants of this packaging, which has been the main force for a long time in the heyday of semiconductor innovation. It is worth noting that most chips have pins on four sides. This follows the general desire of encapsulation to take up less space and increase connection bandwidth or I/O. Every additional progress will take this into account, and it is a model worthy of attention.

This process was once manual, but is now highly automated. In addition, this actually creates quite a lot of problems for PCB, such as popCorning. Package burst refers to that during the welding process, the moisture in the plastic package is heated. Due to rapid heating and cooling, the moisture causes problems on the PCB. Another thing to note is that with each improvement of the packaging process, the complexity and failure will also increase

Ball grid package and chip level package (1990s to 2000s)

With the increasing demand for semiconductor speed, the demand for better packaging is also increasing. Although QFN (square flat leadless) and other surface mount technologies have emerged, I would like to introduce you to the beginning of a package design that we must understand in the future, which is the beginning of the widely used ball grid array (BGA) package.

These solder balls or bumps are called solder bumps/balls

This is the appearance of the ball grid array. You can directly install a silicon chip onto the PCB or substrate from below, instead of simply pasting adhesive tape on all four corners as in the previous surface mount technology.

Therefore, this is just another continuation of the trend I listed above, which takes up less space and has more connections. Now, instead of connecting each side of the package with wires, we directly connect one package to another. This has led to increased density, better I/O performance, and now increased complexity, that is, how do you check whether the BGA package is working. Before that, packaging was mainly through visual inspection and testing. Now we cannot see the encapsulation, so there is no way to test. We can do X-ray inspection and more complicated technology.

Modern packaging (2000-2010s)

We are now entering the era of modern packaging.

Many of the encapsulation schemes described above are still in use today, but you will begin to see more and more encapsulation types, which will become more relevant in the future. To be fair, many of these upcoming technologies were invented in the past decades, but were not widely used until later due to cost reasons.

Flip Chip

This is one of the most common encapsulation you may read or hear about. I'm glad to define it for you, because so far, there is no satisfactory explanation in the introductory books I have read. Flip chip was invented by IBM very early, and is usually abbreviated as C4. As far as flip chip is concerned, it is not an independent packaging form, but a packaging style. It is almost as long as there is a solder bump on the chip. The chip is not bonded and interconnected by wires, but turned over to face another chip, with a connecting substrate in the middle, so it is called "flip chip".

From the explanation on Wikipedia, we can better understand what flip chip is:

1. Create integrated circuits on the wafer

2. The bonding pad on the chip surface is metallized

3. Depositing a solder joint on each pad

4. Chip is cut

5. The chip is turned over and positioned so that the solder ball faces the circuit

6. Then re melt the welding ball

7. The bottom of the installed chip is filled with electrical insulating glue

Lead wire bonding

Note the difference between flip chip and wire bonding. The DIP package described above is called wire bonding, in which the chip is bonded to another metal using wires, and then welded to the PCB. Lead wire bonding is not a specific technology, but a set of older technologies, covering many different types of packaging. Wire bonding is the predecessor of flip chip.

Advanced packaging (since 2010)

We have been slowly entering the era of "advanced packaging" semiconductors. Now I want to talk about some more advanced concepts. In fact, there are various levels of "encapsulation" suitable for this thinking process. Most of the packages we have talked about before are concentrated on chip packaging to PCB, but the beginning of advanced packaging actually starts from mobile phones.

Mobile phones are a huge prelude to advanced packaging in many aspects. This is reasonable! Mobile phones need to integrate a large number of chips in the smallest space possible, which is much denser than laptops or desktops. Everything must be passively cooled and, of course, as thin as possible. This pushes packaging to new limits. Many of the concepts we discussed began with smart phone packaging, and now we have pushed ourselves to other parts of the semiconductor industry.

Chip level package (CSP)

Chip level packaging is actually wider than it sounds, which initially means chip size packaging. The technical definition is that the package size shall not exceed 1.2 times of the chip itself, and must be single chip and connectable. In fact, I have introduced you to the concept of CSP, that is, through flip chip. But CSP has indeed reached a new level through smart phones.

Everything in this picture is 1.2 times the size of the chip and focuses on saving as much space as possible. There are many different styles in the CSP era, including flip chip, right substrate and other technologies.

Wafer Level Package (WLP)

But there is a smaller level -- this is the "ultimate" chip scale package size, or packaging at the wafer level. This is almost putting the package on the actual silicon chip itself. What is encapsulated is a silicon chip. It is thinner, has the highest level of I/O, and is obviously very hot and difficult to manufacture. The advanced packaging revolution is currently on the scale of CSP, but will focus on the wafer in the future.

This is an interesting evolution, the packaging is contained in the actual silicon itself. A chip is a package and vice versa. Compared with just welding some balls to the chip, this is really expensive, so why do we do this? Why are you so obsessed with advanced packaging?

Advanced Packaging: Future

This is the culmination of a trend that I have been describing for a long time. Heterogeneous computing is not only a matter of specialization, but also a matter of how we put all these pieces of specialization together. Advanced packaging is the key driver of all this.

Let's take a look at Apple M1 - a classic heterogeneous computing configuration, especially its unified memory structure. For me, the birth of M1 is not a time of "sensationalism", but a strange time when heterogeneous computing is about to explode.

M1 is sounding the future, and many people will soon follow Apple's example. Note that the actual SOC (System on Chip) is not heterogeneous -- but the custom encapsulation of memory close to the SOC is heterogeneous.

M1 uses 2.5D packaging to directly package the memory to the side of the processing, without PCB wiring,

Another very good example of advanced packaging is Nvidia's new A100. Again, notice that there are no wires on the PCB.

Unlike the traditional GDDR5 GPU board design, HBM2 requires a large number of discrete memory chips around the GPU, but includes a vertical stack of one or more memory chips. The memory chips are connected using tiny wires formed from silicon through holes and micro bumps. An 8 Gb HBM2 chip contains more than 5000 silicon through holes. Then a passive silicon intermediate layer is used to connect the memory stack and the GPU chip. The combination of HBM2 stack, GPU chip and silicon interlayer is packaged in a single 55mm x 55mm BGA package. For the illustration of GP100 and two HBM2 stacks, see Figure 9; See Figure 10 for a photomicrograph of the actual P100 with GPU and memory.

The conclusion here is that the best chips in the world are all made in one way, and this revolution will not stop. Next, we will introduce the two main categories of advanced packaging, 2.5D and 3D packaging.

2.5D package

2.5D is a bit like the turbo version of the flip chip mentioned above, but instead of stacking a single chip on a PCB, it stacks the chips on the top of a single intermediate layer. I think this picture illustrates this very well.

2.5D is like a basement door entering your neighbor's house. Physically, it is a bump or TSV (through the silicon through hole) that enters the silicon plug below you, which connects you with your neighbor. This is not faster than your actual on-chip communication, but because your net output is determined by the overall package performance, the reduced distance and the increased interconnection between two silicon chips exceed all the disadvantages of not having a single SOC.

The advantage of this is that you can use the designed "small chip" to quickly assemble larger and more complex packages. It would be better if it could be done on a silicon chip, but this process makes manufacturing easier, especially on smaller sizes.

"Small chip" and 2.5D package may be used for a long time. It is easier to manufacture and much cheaper than 3D package. In addition, it can be expanded well, and can be reused with new small chips, so that new chips with the same packaging format can be manufactured by replacing small chips. AMD's new Zen3 improvement is just like this, with similar packages, but some small chips have been upgraded.

3D packaging

3D packaging is a "holy grail" and the ultimate end of packaging. It can be said that now, instead of having all the independent small houses with one floor high on the ground and connected by the basement, it is better to have a huge skyscraper, which is customized with any process required for the function. This is 3D packaging - all packaging is now done on the silicon chip itself. It is the fastest and most energy-efficient way to drive larger, more complex structures that are built for tasks and will significantly extend Moore's Law. In the future, we may not be able to obtain more chip size shrinkage, but now with 3D packaging, we can still improve our chips in the future, similar to the previous Moore's Law.

Interestingly, we have an obvious example of the whole semiconductor market moving towards 3D - memory. The promotion of memory to 3D structure is a good illustration of future development. Part of the reason NAND has to adopt 3D structures is that they are difficult to expand in small geometric dimensions. Imagine that the memory is a large 3D skyscraper, and each floor is connected by an elevator. These are called "TSV" or through silicon holes.

This is the future. We may even stack GPU/CPU chips on each other or memory on CPUs. This is the last frontier, and now we are rapidly approaching the frontier. In the next five years, you may start to see 3D packaging emerge again and again.

2.5D/3D Packaging Solution Quick Overview

In my opinion, rather than further understanding 3D and 2.5D packaging, it is better to directly introduce some processes in use that you may have heard of. I would like to focus on the processes made by the wafer factory, which promote the development of 3D/2.5D integration.

TSMC's CoWoS

This seems to be the main force of 2.5D integrated process, which was first introduced by Xilinx.

This process mainly focuses on placing all logic chips on the silicon intermediate layer and then on the packaging substrate. Everything is connected by micro bumps or balls. This is a classic 2.5D structure.

TSMC SOIC

TSMC's 3D packaging platform is a relatively new technology..

Note this amazing chart about bump density and joint spacing. SoIC is not even close to Flipchip or 2.5D in size, but is almost a front-end process in density and feature size.

This is a good comparison of their technologies, but please note that SoIC actually has a chip stack similar to 3D stack, rather than the middle level 2.5D integration.

Samsung XCube

In recent years, Samsung has become a more important OEM partner. Of course, in order not to be surpassed, Samsung has a new 3D packaging scheme. Check out their XCube video below.

There is not much information here, but I want to emphasize that the A100 is made in Samsung technology, so this may be the technology that provides power for Nvidia's recent chips. In addition, samsung may have the richest tsv experience among all the companies here.

Intel Foveros

Finally, the Foveros 3D package of Intel. We may see Intel implement more in the "hybrid CPU" process in the future 7nm and beyond. They have made it very clear on the Architecture Day that this is the focus of their progress.

Interestingly, in the process of 3D packaging, there is not much difference between Samsung, TSMC or Intel.